[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Aug 14 16:44:49 BST 2019


--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #5)
> Note that I did also write a partitioned adder and all partitioned bitwise
> ops (and/or/xor/not, but not shift/rotate/anything that communicates between
> bits) are identical to the non-partitioned ops.
> the partitioned adder should be quite easily updated to an add/subtracter.


Also need comparators GE LE GT LT EQ NE. Can you do those as well?

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list