[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)

> the only thing is: multiply is *not* going to be easy, because it's
> multi-stage.  so i think there, we would have to do something quite
> complex inside the multiply, like:
> 
> class PartitionedSignal:
> 
>    def __mul__(self, value):
>        if self.ctx.operator == FIRST_STAGE_MULTIPLY:
>            # do wallace multiply step 1
>        elif self.ctx.operator == SECOND_STAGE_MULTIPLY:
>            # do wallace multiply step 2
> 
> or something like that.  needs thought.

all the other operators will be single-cycle so are not a problem.

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