[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
for the dynamic partitioning (SIMD ALUs) we need a way to break a signal at
runtime into parts.  we already have a "multiply" operator that can do that,
however what if we took that to the logical extreme and made *all* operators
partitionable?  add, compare, or, shift, len - everything that's in the
Value class.

the alternative is to complicate the layout of existing pipelines through
explicit creation of dynamically-partitioned "clones".

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