[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal

lkcl luke.leighton at gmail.com
Tue Aug 13 05:32:55 BST 2019

On Tuesday, August 13, 2019 at 2:05:23 AM UTC+1, MitchAlsup wrote:
> The alternative is to designate a few OpCodes in a sequence as a single 
> result producer, with the intermediate result kept larger than register 
> width and fed back to the in-sequent instruction (preserving accuracy.)

yehyeh, i totally get it / like it, as a design concept.  the implications 
however are for context-switches (which you can "fudge" in a dedicated GPU 
as it's not going to be dealing with other general-purpose tasks, but you 
can't really do in a Hybrid CPU/GPU), the intermediate registers would need 

that in turn puts pressure on the register file size, which is already big 
for a GPU.  or requires a "special" register file, other than FP, INT (and 
in some cases V as well).  which in turn requires _more_ opcodes to... yeh, 
you get the idea :)

which is why i said that starting from RISC-V, for GPU purposes, isn't 
necessarily the smartest thing to do / be constrained by.

ho hum :)


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