[libre-riscv-dev] [hw-dev] IEEE754FPU pipeline API and its use

[Jacob Lifshay]

On Tue, Aug 6, 2019, 01:04 lkcl <luke.leighton at gmail.com> wrote:

> The features missing which are under development are tininess, rounding
> modes, FP flags, FMAC (complicated), FSGN (trivial to do), and the addition
> of multi stage multiply so that it is not necessary to have a full 53 bit
> multiply unit producing a 108 bit result in a single cycle.
>
additionally, we do have a working pipelined dynamically-partitionable
8x8/16x4/32x2/64x1 SIMD integer multiplier that is intended to fit into the
fp multiplier/mul-adder, it just hasn't been integrated into the fpu yet.
https://salsa.debian.org/Kazan-team/simple-barrel-processor/blob/master/src/multiply.py

Jacob