[libre-riscv-dev] ALU ported over from Verilog to nMigen
Samuel Falvo II
sam.falvo at gmail.com
Sun Aug 4 23:16:38 BST 2019
The code has no accompanying tests yet (it will take some time to translate
the Verilog unit tests over to nMigen). But, might be worthy of a gander
to those interested.
nMigen's code is significantly more verbose than Verilog in this case, even
without considering the new set of comments to explain how the stuff works.
Samuel A. Falvo II
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