[libre-riscv-dev] ALU ported over from Verilog to nMigen

[Samuel Falvo II]

http://chiselapp.com/user/kc5tja/repository/kestrel-3/artifact/231dc2c2884b58d6

The code has no accompanying tests yet (it will take some time to translate
the Verilog unit tests over to nMigen).  But, might be worthy of a gander
to those interested.

nMigen's code is significantly more verbose than Verilog in this case, even
without considering the new set of comments to explain how the stuff works.

-- 
Samuel A. Falvo II