[libre-riscv-dev] [Bug 64] data handling / io control / data routing API needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=64

--- Comment #43 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #39)
> (In reply to Luke Kenneth Casson Leighton from comment #22)
> > (In reply to Jacob Lifshay from comment #8)
> > 
> > > > * Data.eq not Data.assign is better, although just "eq" is preferred
> > > >   (which can be used as "from import library import data" then
> > > > "data.eq(...)")
> > > I'm using Data as a place to stash lots of Data-related static functions. We
> > > can switch to a module if you like.
> > 
> >  temporarily nmoperator.py (would like it to be e.g. nmutils.operator)
> > 
> >  http://bugs.libre-riscv.org/show_bug.cgi?id=68
> > 
> >  amazingly, only 3 or 4 actual functions are needed.  eq, shape and cat
> >  are three key functions:
> > 
> >  * eq is obvious [at least, if nmigen's eq is understood, it's obvious]
> > 
> >  * shape and cat are needed in order to flatten data down and back out
> >    to and from a straight signal.
> > 
> >  shape and cat get used inside the FIFOControl object (which in turn
> >  uses that excellent Queue module that you wrote).
> I don't think we should use nmigen's FIFO interface, having an interface
> like was in the original Chisel code with a separate enq (entry) and deq
> (exit) port means that Queue is a Block rather than changing Queue to fit
> nmigen's FIFO interface only to then need to adapt back to the 2-port
> interface everywhere.

 they're all 2-port interfaces, all of them.  Queue, Block, ControlBase,
 Chisel's code, FIFOInterface, they all have exactly the same incoming
 ready/valid/data and outgoing ready/valid/data ports.

 where did you get the impression from that they don't have the exact
 same port-semantics?

 Queue-to-FIFOControl (a derivative of ControlBase aka Block-esque):

         connections = [self.n.valid_o.eq(fifo.readable),
                       fifo.re.eq(self.n.ready_i_test),

 valid_o EQUALs readable.  fifo.re EQUALs ready_i.

 there's literally no change in the logic.  there's no change made.  there's
 no "if ready == True and valid != something set readable True".

 it's a DDDDIIIIRRREEEECCCCCT eq assignment, on *ALL SIX* signal-sets
 (ok except the data goes through process() and happens to get flattened
  and de-flattened).

 can you see that FIFOControl is *LITERALLY* just a wrapper around Queue?

 can you see also that Queue has, from the original Chisel3 code, ONLY
 had the names of the variables changed, *NOT THEIR FUNCTION IN ANY WAY
 SHAPE OR FORM*?

 i *literally* transcribed the code from the original conversion that you
 did, and *ONLY* did a global/search/replace of the names, to match
 FIFOInterface.

 FIFOInterface ***IS*** Queue.  Queue ***IS*** FIFOInterface.

 i can't think of a way to emphasise clearly enough how these are literally
 identical except for the change in names.

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