[libre-riscv-dev] [Bug 64] data handling / io control / data routing API needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=64

--- Comment #36 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #9)

> > this down to the fact that the FSM must *only* permit a single clock
> > of "ready/valid" on its input, and must *only* permit a single clock
> > of "ready/valid" on its output.
> Actually, a FSM isn't limited to a data-transfer every other clock, as is
> evidenced by the fact that every digital logic circuit with only one clock
> and no combinatorial loops is a FSM, either a Mealy FSM or a Moore FSM.

 ... so... this is useful definitions... the FPDIV code is a...
 hang on let me check the wikipedia page, damn their names both begin with M.
 Mealy.  the FPDIV code is a Mealy FSM.  not pure combinatorial.

> The part that is limiting stb/ack (from what you told me) is that ack has to
> be de-asserted after every transfer.

 ah this may be a.. ok, so read again here:
 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html

 the data is transferred on every clock where READY=TRUE and VALID=TRUE.
 or, more to the point, it is *required* that data be accepted when those
 conditions are true.

 so if there are two clocks in which those conditions are true, we can
 logically deduce that *TWO* pieces of data have been transferred.

 thus, if ACK is *NOT* de-asserted, and the user happens accidentally to
 leave STB asserted, *TWO* pieces of data will be transferred into the FSM...

 ...one of which will be DESTROYED.

 if the FSM was not an FSM, it would be capable of receiving data on
 each and every clock, letting data in by leaving ACK high.

 now, we could indeed have two separate FSMs, one for input and one for
 output, however that's just not how this *particular* example has been
 designed.

 that does not mean that a twin-FSM could not be designed: it's just that
 this particular one has not.

 i am going to see if further topological morphing can make the FPDIV
 example conform to the Stage API.  i believe it can.

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