[libre-riscv-dev] [Bug 74] preliminary exploratory software emulation of FP SQRT

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=74

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Aleksandar Kostovic from comment #4)

> it supports ** operator
> 
> so now i am not yet sure but i think this should be able to reduce the
> amount of work needed to produce sqrt function.

as jacob said: i think that's usually used to do 2**3 (integer powers,
basically).

hardware is so low-level, i was actually extremely surprised to find
that verilog supports integer-divide.

can i suggest the first step being to convert that c-code from the paper
into python, or to convert the one from jacob's code (it's a lot simpler).
if i remove the brackets and leave in the indentation it's almost done
already!

        for(; bit != (fixed_width_uint)0; bit = bit >> 2)
            if(v >= bit + retval)
                v = v - (bit + retval);
                retval = (retval >> 1) | bit;
            else
                retval = retval >> 1;

just literally clean that up, add it to the repo somewhere, run it,
make it work, and play with it.

put in some values, see what it does, run it again.

then you will start to get confidence in python and in sqrt.


> Plan is to re-use get_a and get_b functions, add another func called sqrt in
> the FSM, then add normalise funcs

yes that would do the trick - bear in mind that's the hardware, where
this bugreport is for discussion of the software simulation side.
so, that should be discussed further under bug #43

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