[libre-riscv-dev] [Bug 48] Complete IEEE754 floating point pipeline

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=48

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/nmigen_div_experiment.py;hb=HEAD#l158

relevant code:

 161                     div.quot.eq(div.quot << 1),
 162                     div.rem.eq(Cat(div.dend[-1], div.rem[0:])),
 163                     div.dend.eq(div.dend << 1),

and:

 172                 with m.If(div.rem >= div.dor):
 173                     m.d.sync += [div.quot[0].eq(1),
 175                                  div.rem.eq(div.rem - div.dor),]
 177                 with m.If(div.count == div.width-2):
 178                     m.next = "divide_3"
 179                 with m.Else():
 180                     m.next = "divide_1"
 181                     m.d.sync += div.count.eq(div.count + 1),

so the way i see it, it's hardly even worth sub-classing.

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