[libre-riscv-dev] [Bug 76] New: IEEE754 RISC-V "tininess" as well as rounding modes (odd/even) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=76

            Bug ID: 76
           Summary: IEEE754 RISC-V "tininess" as well as rounding modes
                    (odd/even) needed
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: ALU (including IEEE754 16/32/64-bit FPU)
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

RISC-V has some specific "quirks" in its handling of rounding,
tininess and NaN handling, which need to be specifically catered for.

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