[libre-riscv-dev] [Bug 64] data handling / io control / data routing API needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=64

--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> i thought about the FSM case, that the stb/ack is at a "disadvantage"
> due to it being 2-cycle acknowledgement... and it occurred to me
> that this is just a natural consequence of an FSM within a ready/valid
> prev/next pair.
> 
> in other words: even a FSM placed within a ready/valid prev/next pair
> *has* to fall back to 2-cycle behaviour, and, in fact the names stb/ack
> *are* ready/valid.
> 
> this down to the fact that the FSM must *only* permit a single clock
> of "ready/valid" on its input, and must *only* permit a single clock
> of "ready/valid" on its output.
Actually, a FSM isn't limited to a data-transfer every other clock, as is
evidenced by the fact that every digital logic circuit with only one clock and
no combinatorial loops is a FSM, either a Mealy FSM or a Moore FSM.

The part that is limiting stb/ack (from what you told me) is that ack has to be
de-asserted after every transfer.

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