[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
module fsm
  #(
    parameter AXI_M_ADDR_WIDTH = 40,
    parameter AXI_S_ADDR_WIDTH = 32,
    parameter AXI_ID_WIDTH     = 8,
    parameter AXI_USER_WIDTH   = 6
  )

-->

class fsm:
    def __init__(AXI_M_ADDR_WIDTH=40, AXI_S_ADDR_WIDTH=32, AXI_ID_WIDTH=8,
AXI_USER_WIDTH=6):

woo!

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