[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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           Assignee|lkcl at lkcl.net               |programmerjake at gmail.com
                 CC|                            |programmerjake at gmail.com

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
what do you think of writing a tool in Rust that uses yosys to convert the
verilog to ilang, then yosys prints out json, which we can use the serde
library to parse and then print python and finally use a python code formatter
to format it?
If we do it that way, we can have yosys, serde, and the python formatter do all
the hard parts

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