[libre-riscv-dev] [Bug 71] replace SetAssocCache PLRU with random selection (LFSR)

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=71

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
it goes something like this:

* cset is the address (passed to N banks of memory, simultaneously)
* cset also goes into the PLRU to generate an arbitrary N (one of the mem
banks)
  where there is one PLRU *per cset* (so... lots of them)
* the incoming tag is dropped into the data that's stored in the selected bank
* active bit is set as well (bit 0 of the actual data stored in the Memory)

to read:

* hit *all* N banks with the cset address and the tag
* ask all banks to read and see if the tag-bits match the requested tag
* if so, and the active bit is also set in the bank, return data.

so... what you are saying, jacob, is that a random selection of which bank
to use is fine, no need to check if any of the banks are full or not.

i have seen on google searches that both algorithms are sometimes used.
am curious as to why.

-- 
You are receiving this mail because:
You are on the CC list for the bug.