[libre-riscv-dev] pipeline sync issues

[Jacob Lifshay]

I looked at the Queue class in Chisel's standard library, and it has a
ready/valid interface exactly equivalent to what I had written for the
ready/valid Stage API, except that Chisel uses the name "bits" instead of
"data" and Chisel splits the ready/valid interface into two types:
DecoupledIO and IrrevocableIO.

>From what I can tell by reading the code, Queue with entries=1, pipe=true,
and flow=false is logically equivalent to RegStage and Queue with
entries=1, pipe=false, and flow=true is logically equivalent to
BreakReadyChainStage. I am translating Queue to nmigen to verify that
equivalence by comparing the Verilog output.

IrrevocableIO is different from DecoupledIO in that it gives the following
guarantee (quoted from docs):
    A concrete subclass of ReadyValidIO that promises to not change
    the value of 'bits' after a cycle where 'valid' is high and 'ready' is
low.
    Additionally, once 'valid' is raised it will never be lowered until
after
    'ready' has also been raised

Jacob