[libre-riscv-dev] pipeline sync issues

[Luke Kenneth Casson Leighton]

http://bugs.libre-riscv.org/show_bug.cgi?id=57#c6

ok i think i have the answer as to why UnbufferedPipeline (CombStage),
and UnbufferedPipeline2 (BreakReadyStage) etc. are not working.

i wrote out the truth table and found that UnbufferedPipeline does not
take into consideration p_o_ready.

setting p_o_ready on any given cycle is a *contract* that says that,
on the *next* cycle, if n_i_valid is true the stage *WILL*, without
fail, be ready to accept the input.

to reiterate: that's on the *next* cycle it will be ready to accept the input.

in terms of e.g. the nmigen FIFO code, it's similar to as if
write-enable were ignored.

by contrast, the truth table for SimpleHandshake respects p_o_ready.
it takes into account all four signals, and is a 16-way table.
UnbufferedPipeline is only 8, which is a clear indicator of the source
of the issue.

l.