[libre-riscv-dev] pipeline stages controlling delays

[Luke Kenneth Casson Leighton]

https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v

gave up trying to randomly guess and created a new pipeline class
based on the above, which turns out to be the logic handling from
wishbone and AXI4.  very very fortunately, the transformation was
successful.

there are two very interesting aspects to it:

(1) the ready signals are a pass-through.  incoming ready from next is
*directly* (combinatorially) passed out to previous.  this is quite a
surprise, given how the buffered handshake is such a complex state
machine.

(2) the conditions under which data may continue to be sent even when
the previous stage no longer has anything are very clear, meaning that
there's potentially an additional extension to the API here, to allow
that.  it is however going to need some thought.

the relevant line is this one:
https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v#L78

what that's saying is, "# previous invalid or not ready, however next
is accepting, *CONTINUE* sending data from an internal FIFO until it
is empty". the way that the hbdeword.v example works is, the data is
received 32 bits at a time but *only 4 at a time are sent*.  it's
quite fascinating and would also be a useful example to create.

lots and lots to think about here.

l.