[libre-riscv-dev] pipeline stages controlling delays

[Luke Kenneth Casson Leighton]

On Sat, Apr 6, 2019 at 9:06 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

>  it would be much more productive to help me track down the two-stage
> pipeline bug (buf + unbuf) - Test 999, and help me to track down why
> Test 14 is failing.

http://bugs.libre-riscv.org/show_bug.cgi?id=59

i've created a side-by-side annotation of a case where the d_ready and
d_valid signals are asserted for one clock cycle, only one clock apart
(succeeds), where when that is extended to two cycles apart it fails.

much of what i am doing here is literally pure guesswork.  inserting
this extra condition, see if that works, no it didn't let's try
another extra AND or OR or NOT statement, see if that works, repeat,
repeat, repeat, repeat.

could people take a look as i am really struggling to understand
what's going on.

l.
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