[libre-riscv-dev] pipeline stages controlling delays

[Luke Kenneth Casson Leighton]

On Fri, Apr 5, 2019 at 11:44 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> ok.... so... i am guessing that the same trick needs to be applied to
> the output.

 ... it was... sort-of the trick is to pretend that n.i_ready is false
if the data is not ready.  so it's kinda a mirror, with the added
complication that n.i_ready is set externally.

also given that there's "d_ready", i renamed "p_o_valid" to "d_valid"
to make it clear that it's associated with the data, not the control
logic.

not out of the woods yet, a 2-stage pipeline failed (where a single
pipeline works).  will get to your reply next, jacob.

l.