[libre-riscv-dev] need help with auto-pipeline stage creation

[Luke Kenneth Casson Leighton]

On Wed, Apr 3, 2019 at 9:15 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> try printing the list of assignments and looking for the missing ones.
> __repr__() on Assign is overloaded to show what's being assigned where.

 i've augmented signal's __repr__ to add the DUID: i'm still getting
completely lost.
l.