[libre-riscv-dev] simple barrel processor pipeline design diagram

[Luke Kenneth Casson Leighton]

On Wed, Apr 3, 2019 at 7:24 AM Jacob Lifshay <programmerjake at gmail.com> wrote:

> > question: is it necessary to have RS1 and RS2 be in different stages?
> > if the regfile is 2R1W it should be able to handle 2 simultaneous
> > reads, RS1 and RS2.  or, is that done just to be able to get 5 cycles?
> >
> It's done to allow regfile to be split into 5 separate banks, each bank has
> a single read/write port. If both reads were done in the same cycle, then
> the regfile banks would need to be dual-ported (increasing area and power
> by a lot).

 the reads (and writes) will still be at the single (main) clockrate
though.  they're not done in parallel.  so in theeeoryyy... the only
thing holding things back would be the area.... ok, yes, i see: 5x the
register file size, of 2R1W SRAM rather than 1R1W, got it.

l.