[libre-riscv-dev] Fwd: Preparations The Libre-RISCV SoC

[Jacob Lifshay]

fix typo on "shocklngly"

On Sun, Mar 31, 2019, 20:05 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> minor edits, i went with this, below.  prior draft forgot mention of
> RISC-V, also replaced "but also" with "and".
> sent.
>
> -----
>
> It is 2019 and it is not possible to buy a mass-produced laptop, tablet
> or smartphone and replace all of its software (with software that a
> user can trust) without loss of functionality.  Processor boot-loaders
> are DRM-locked; WIFI, 3D Graphics and Video Processors are proprietary,
> and Intel's processors contain NSA-spying backdoor "Management" Engines.
>
> Therefore, shocklngly, the only way to restore and engender trust is
> to literally make a new processor - one that is developed transparently
> and may be independently audited to the bedrock.
>
> So we are developing a a low-power, mobile-class, 64-bit Quad-Core
> RISC-V SoC at a minimum 800mhz clock rate, suitable for tablet,
> netbook, and industrial embedded systems. Full source code files
> are available for the operating system and bootloader, and the actual
> processor, its peripherals and its 3D GPU and VPU.  Details at
> http://libre-riscv.org/3d_gpu/
>
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