[libre-riscv-dev] Fwd: spike simple-v implementation, refinement needed

[Luke Kenneth Casson Leighton]

ok got predication working: it's getting to be really hair-raising
code, as it's a state machine, not a straightforward "if then else"
around a loop: the loop can be terminated based on predication
conditions and other things.

really it's time to start writing unit tests as it's getting
complicated.  also i've noticed that some opcodes must not be
parallelised: lui, csr* and there are almost certainly going to be
others.  some others (ebreak etc.) do not use registers so are
inherently non-parallelised, however it's clearly unsafe to
parallelise lui,

csrrw etc. really should not be parallelised, although a case could be
made for incrementing the CSR so that multiple CSRs could be
saved/stored from registers... have to think about that one.

l.