[libre-riscv-dev] spike-sv elwidth support for floating-point

[Luke Kenneth Casson Leighton]

ok so the elwidth support for register read and write, as well as load
and store, is now implemented in spike-sv.  a unit test for VL=2 FP16
single-precision add has been demonstrated to actually perform 2 FP16
adds instead of 2 FP32 adds.

or so it seems.

where for the integer operations i decided to actually have each
operation do (where needed) a reduced width operation (where as we
discussed a month ago, many of them won't, exceptions being div and
sr), for the FP ones it's too complex and too comprehensive to do
that, so instead i decided to *convert* at the point of transfer.

so the actual FP operations are carried out internally at the standard
explicit sized: fp128_add still does operations at and on 128-bit
operands.  it's just that whenever there is a conversion from fp128 to
fp32 for example, that's over-ridden to down-convert to fp16 instead.

the tricky bits will be the corner-cases, FMV, FCVT, and the
conversion from int to fp and so on.

however, the big thing is: it's underway, with FP16 adds being successful.

still a lot to do, including overrides on f128 and f64.

l.