[libre-riscv-dev] spike-sv non-default element widths

[lkcl]

On Fri, Oct 26, 2018 at 1:43 AM lkcl <lkcl at libre-riscv.org> wrote:
>
> okay!  at last, retrieving / storing to registers (integer only at the
> moment) actually works, with a c.mv preliminary test, on bit-widths of
> default (xlen), 8, 16 and 32.  i've yet to put in sign/zero-extension,
> that's going to be interesting / tricky and i may need some help.

 ok first couple of unit tests are in (add and addw), and it's looking
good so far.  the unit tests picked up a bug where i had forgotten to
mask off the high bits of the data being spliced into the result
register.

 the add test checks the zero-extension, the addw tests sign-extend.

l.