[libre-riscv-dev] spike-sv non-default element widths

[lkcl]

https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=blob;f=operators/operators.t.cc;h=3ad5c68fe80d53ed8546358856d4b4647c8dc8ec;hb=ca25e0e1b818b48a33e96bba668d439abc06ad33

ok much more explicit, here.  macros are gone for div, rem, sll and
srl, replaced by the actual algorithms from the corresponding
insns/*.h.

shiftl works if you over-ride xlen so that the algorithm is:
                x1 = (uint8_t)x;
                y1 = (uint8_t)y;
                uint64_t z1 = (x1 << (y1 & (8-1)));

shiftr works same:
                int8_t z = 0;
                z = (int8_t)(zext(x, 8) >> (y & (8-1)));
                x1 = (uint8_t)x;
                y1 = (uint8_t)y;
                uint64_t z1 = (zext(x1, 8) >> (y1 & (8-1)));

remainder works if you have the same checks.

divide is a pain, it will need a #redefine of UINT64_MAX and INT64_MIN.  div.h:

if(rhs == 0)
  WRITE_RD(UINT64_MAX);
else if(lhs == INT64_MIN && rhs == -1)

and SLLW is not going to work at all:
WRITE_RD(sext32(RS1 << (RS2 & 0x1F)));

that 0x1f needs some thought.

l.