[libre-riscv-dev] register requirements of SimpleV

[Luke Kenneth Casson Leighton]

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On Tue, Oct 9, 2018 at 11:18 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> or.... argh, there isn't.  regidx becomes 7-bit, that's now 16.  sigh
> i could lose the "active" bit, that would do the trick.
>
> ok, 7 bits it is - let me sort that out.

 done: unit tests pass, macros altered.  TODO: update the spec.

 implications are that it's now a little weird to do "packed SIMD"
mode.  i think... ok, i got it, what you do is this:

        uint64_t     regkey: 5; set to 1-31
        unsigned int zero  : 1; set to FALSE
        unsigned int inv   : 1; set to **TRUE**
        unsigned int type  : 1; set as required
        uint64_t     regidx: 7; set to **ZERO** (i.e. x0)
        unsigned int packed : 1; set to TRUE

in that way, by saying "if you use register x1-x31 anywhere, you get
to use the INVERSION of x0 as the predicate", that would result in the
predicate being set to 0xffffffff, which is *equivalent* to "no
predication at all", and "packed SIMD" just happens to be set.

l.