[libre-riscv-dev] register requirements of SimpleV

[Luke Kenneth Casson Leighton]

ok i went for a nice walk, and after about 5 circuits of the park i
had an idea: move the "packed SIMD" bit field from the register CSR
CAM table into the predication CSR CAM table.  this would be possible
because there is *just* the one bit left in the predication CSR table:

union sv_pred_csr_entry {
    struct {
        uint64_t     regkey: 5; // 5 bits
        unsigned int zero  : 1; // zeroing=1, skipping=0
        unsigned int inv   : 1; // inversion=1
        unsigned int type  : 1; // 1=INT, 0=FP
        uint64_t     regidx: 6; // 6 bits
        unsigned int active: 1; // enabled=1, disabled=0
    } b;
    unsigned short u;
};

or.... argh, there isn't.  regidx becomes 7-bit, that's now 16.  sigh
i could lose the "active" bit, that would do the trick.

ok, 7 bits it is - let me sort that out.

l.