[libre-riscv-dev] SV spec: C.LDSP/C.LWSP and other LOAD/STORE operations

[Luke Kenneth Casson Leighton]

ok so if SV is to be able to support interaction with memory in a
parallel-looking fashion, where a single instruction can "issue"
multiple loads and stores, then there could potentially be a page
fault in the middle of that loop, which complicates matters
considerably.

this ideally implies that LOAD/STORE needs to be re-entrant, and i
believe i have a potential way to implement that.  the pseudo-code
always has an offset: the "loop" variable which is implicitly added to
the register number being used, so as to make it look like one
instruction is actually several.

if that offset was actually a CSR that could be both read and written,
it would be possible to do both save and restore of the full execution
state, even if the processor was in the middle of executing a parallel
loop.

the alternative would be that the processor would need to "pre-issue"
LOAD / STORE operations, perhaps by trying them out with x0, first,
and then making absolutely sure that the cache lines were pinned.

another alternative would be to have hardware-level page TLBs and so
on where it was absolutely guaranteed that page-faults would be
entirely handled by hardware.  i'm not happy for SV to place such a
burden on implementors (setting such a high microarchitectural bar).

anyone got any other ideas?  i'll ping isa-dev as well.

l.