[libre-riscv-dev] Fwd: spike simple-v implementation, refinement needed

[Luke Kenneth Casson Leighton]

ok i have some unit tests now, here:
https://git.libre-riscv.org/?p=riscv-tests.git;a=shortlog;h=refs/heads/sv

the tests so far are vector-immediate (same src/dest), scalar-vector,
predicated (zeroing and inversion), and redirection: deliberately
setting a register x16 to point at x3.  i have one more
(vector-vector) i want to do, then i can move on to something else:
that series (using addi) is basically done.

a good next one to do would be floating-point, and then fvct, just to
check that the spike-sv register-detection i had to put in can in fact
cope with floating-point, and also that it can cope with *both* fp
*and* integer.

l.