[libre-riscv-dev] HDL selection

[Luke Kenneth Casson Leighton]

another potential option is ariane:
https://github.com/pulp-platform/ariane

which has superb documentation:
https://pulp-platform.github.io/ariane/docs/id_stage/

however it can only do single-core due to missing atomic according to this:
https://abopen.com/news/pulp-releases-64-bit-linux-compatible-ariane-risc-v-core-ip/

it's in verilog, so it'll be reasonable to understand.


about rocket-chip: i know i said it would be great to start from
somewhere that's working... i am literally unable to read lines of
chisel3 code.  i can just about make out how AMOALU.scala works, for
example.

it is a frickin enormous amount of work to do a new core, however if
the code's not actually readable, or if we spend more time trying to
understand it than modify it, we might as *well* start from scratch,
and, at least that way, we will understand what we are doing.

that being the case, i could easily convince myself to go with migen,
for the reasons you say: it's possible to use the full OO power of
python, where myhdl simply can't (i did try, on the pinmux project:
total fail).  as i've been using python since 2000 it is a no-brainer
decision.

l.