[libre-riscv-dev] [RFC] SV FEQ / FLT / FLE

[Luke Kenneth Casson Leighton]

i just realised that there's a discrepancy between FEQ and BEQ, when
vectorised.  a normal scalar FP branch is like this:

FEQ x1, f1, f2
C.BEQZ x1, #location

(or BEQ x1, x0, #location)

where FEQ will set a 0 or a 1 into integer register, x1.  the problem
is that BEQ has had its rd turned into a bitfield, and i had forgotten
to modify FEQ and friends to *output* a bitfield.  however... it's
also necessary to preserve "pre-existing" behaviour of Base RV.

so, what i plan to do is:

* if FEQ/FLT/FLE destination register is marked as a scalar (or has no
SV CSR entry), multiple compares (VL>1) will treat rd as a bitfield.
* if FEQ/FLT/FLE destination register is marked as a vector, multiple
compares (VL>1) will put zero or 1 into *contiguous* registers rd,
rd+1 ... rd+(VL-1)

thoughts appreciated: again, public discussion *only*, so that the
above may *not* be patented (published prior art), and any patents
that *are* applied for may be invalidated by the timestamp of
publication.

l.