[libre-riscv-dev] 1R1W regfiles
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Dec 21 09:45:08 GMT 2018
* separate 32-bit FUs and 8-bit FUs
* *two* adjacent 32-bit FUs required to provide their src1,src2 values
to do 64-bit ops
* *two* adjacent 8-bit FUs required likewise for 16-bit ops
* cross-blocking on register matrices for 32-bit ops blocking 8-bit
ops and vice-versa
* byte-level crossbars (4x4) are subsumed into xBitManip ALUs
(xBitManip can do full 4-to-4 byte routing)
no need for a totally separate (absolutely massive) 16 by 16
we *may* still be able to allocate multiple 16/8-bit operations down
the 32-bit FUs (as SIMD operations), using the 8-bit FUs for the
corner-cases (and also for xBitManip).
FUs all have src1/src2 (and in some cases src3 as well), with latches.
the read of 2R1W on the regfile needs to be redirectable to the issue
phase (from *either* port) as a top priority (otherwise it holds up
instruction issue), and all of src1, src2 *and* src3 i think we'll
find need to be able to read from either port1 or port2 of the
regfile, as well.
so we will need some sort of regfile queue / redirection - yet another
multiplexer in effect.
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