[libre-riscv-dev] GPU design

[Jacob Lifshay]

On Fri, Dec 7, 2018, 05:13 lkcl <lkcl at libre-riscv.org wrote:

> On Fri, Dec 7, 2018 at 12:52 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> >
> > On Fri, Dec 7, 2018, 04:48 lkcl <lkcl at libre-riscv.org wrote:
> > >  i think, with ROB#s, MV could hypothetically be implemented as
> > > just... changing the dest target register number (and type, from
> > > int/float).  maybe.  will need to be thought through properly.
> > >
> > Yeah, but not needing the mv instruction at all is better.
>
>  it's starting to deviate outside of what RISC-V is/does, and has
> knock-on implications for the compilers which make me very very
> nervous.  jacob bachmeyer already warned me about the Hell That Was
> SSE.
>
Actually, i'm pretty sure he meant mmx. sse is what's currently used for fp
by default for amd64 and it works just fine. The problem with mmx is that
it shares registers with the x87 fpu which uses the registers as an
8-element stack with all the fp instructions accessing registers relative
to the top of stack, whereas the mmx instructions ignore the top of stack.
That causes problems because there was no way to ensure that the stack
didn't overwrite whatever mmx registers were in use, so that made the
registers effectively unusable for fp when mmx was in use and unusable for
mmx when fp was in use. There's even a special emms instruction to reset
the registers so they can be used for fp again.

In my proposal, the registers can be easily used for both at once since
it's trivial to have the register allocator allocate different registers
for different variables. This is similar to the reason that RV doesn't need
dedicated address registers for all pointer-valued variables: it's trivial
to share the registers with integer-valued variables.

Jacob

>